A high-performance chip with dataflow architecture for attitude and heading reference system accelerating

Based on parallel processing methodology, a new design of high-performance chip with data flow architecture for accelerating AHRS is presented in this paper. Based gradient descent algorithm, we divided the serial algorithm into four primary pipeline function blocks on chip: Communication Block, Quaternion Initialization Block, Register file Block and Quaternion Update Block. Every block was constructed with several parallel pipeline channels and embedded a number of acceleration units. Acceleration units were the technical-designed cells working for special mathematical operation, high speed reading and writing process, such as floating point operation, multi-dimension vectors computation and high speed cache on chip, which is proven as a great assistance for the data flow process. Compared to the traditional method estimating by serial MCU architecture, this data flow architecture got nearly a 10 times resolution of accuracy. Meanwhile, the speed of estimation could be raised up to over 40 times.