Annealing temperature optimization for high-performance carbon nanotube thin film transistors

The effect of annealing treatment on the device performance of carbon nanotube thin film transistors (CNT-TFTs) have been investigated systematically. The optimized annealing temperature has been found out from the tradeoff between source-drain total resistance and on-off current ratio, resulting in high-performance CNT-TFTs with a typical I
_on
/I
_off
larger than 10
⁶
, a subthreshold swing as low as 140 mV/dec and a threshold voltage of -0.2 V. When the annealing temperature increased from 300 °C to 400 °C, the device mobility reached 9.7 cm
²
/vs while I
_on
/I
_off
decreased to 10
⁵
. After annealing of 450 °C or above, the off current increased abruptly due to the appearance of metallic nanotube pathways, which can be improved by the electrical breakdown.