Key process development on 300mm wafer for 2.5D/3D integration

2.5D/3D integration has been attracting both academic and industry interests for extending the Moore's Low in recent years and several products using such technology have been emerged. This paper introduces the development progress of key process modules for 2.5D/3D IC integration on our 300mm platform. Experiment results for high aspect ratio TSV formation, fine-pitch RDL & bumping, low cost backside TSV revealing, and wafer level conductive bonding are given. The application of 2.5D/3D TSV integration is also discussed.