A 12-bit 20-MS/s SAR ADC with improved internal clock generator and SAR controller

A 12-bit 20-MS/s charge redistribution successive approximation register analog-to-digital converter in a 65-nm CMOS technology is presented in this paper. To address the issue of long DAC settling time in bit-conversion, an improved internal clock generator is proposed. In addition, a novel SAR controller is introduced to minimize the critical path and improve the conversion speed. Simulation results show that the ADC achieves SNDR of 69.6 dB and SFDR of 79.9 dB with a 9.82-MHz sine-wave input while dissipating power consumption of 2.1 mW from a 1.2-V supply.