Simulation and verification of DDR3 SourceSynchronous clock system based-on SystemSI

In order to calculate the time series of source synchronous clock system, it is critical to sort out the full path that clock and data signals pass. Firstly, there is an analysis on relatively simple common clock system and a detailed description about the structure and timing margin of source synchronous clock system. Finally, taking the on board DDR3bus in high-speed circuit, which comes from our project, as an example, we validate DDR3 source synchronous clock system by the use of System SI, making the timing analysis in source synchronous clock system more streamlined and intuitive. In this paper, a new and effective analysis method applied to timing integrity of high-speed bus in the high-speed PCB design is provided, which can greatly reduce the risk and cost in the development.