A new approach for mixed bandwidth deterministic communication using Ethernet

A new approach for the deterministic communication of real time and Non-Deterministic communication of non-real time traffic on a common Ethernet node is presented in this paper. The design strategy uses the full duplex communication with a switched ethernet technology. The transmission of packets is performed using the major and minor frames concept of cyclic schedulers, wherein each major frame is divided into two logical sub-major frames. The first sub-major frame consists of periodic minor frames of different configurations with deterministic traffic and the second sub-major frame contains aperiodic minor frames with standard ethernet traffic. Thereby achieving both real time and non-real time traffic communication over a single channel, this can be used in avionics, automobiles and automation industries. The major frames are transmitted periodically to achieve the defined time constraints. The IP core for the proposed approach has been developed using the Xilinx tools and can be implemented using a Xilinx SP605 FPGA evaluation board, which is connected to an end system for controlled transmission at 100Mbps.