CMOS roadmap analysis from the perspective of III-V technology using MASTAR

III-V materials are an attractive option for next generation MOSFET devices, essentially thanks to their excellent transport properties. The aim of this work is to benchmark the performance of III-V MOSFET technology (considering In
_0.53
Ga
_0.47
As as the channel material), using the MASTAR [1] platform which includes tunneling effects, mobility physical models, ballistic transport, band-structure modification, short-channel effects, series resistance, parasitic capacitances and accurate current compact model (Fig. 1) [2]. Based on this benchmark, the inclusion of III-V MOSFET in the roadmap will be discussed. Two architectures are considered, Double-Gate (DG) and Nanowire (NW).