Challenges of 3D VLSI-CoolCubeTM process with p-Ge-OI and n-InGaAs-OI for ultimate CMOS nodes

In this paper, we evaluate the various technological solutions and roadblocks for co-integrating p-Ge and n-InGaAs MOSFETs in a 3-D monolithic CoolCube
^TM
technology. In particular, the process sequence (Ge-p-MOS-1
^st
or III-V-n-MOS-1
^st
) is examined in the light of thermal budget limitations arising from junctions definition.