A reduction scheme to optimize the Wallace multiplier

A novel bit-product reduction scheme for an n by n bit Wallace multiplier is proposed in this paper. The proposed scheme differs from the traditional Wallace method in two ways: (1) it redefines the way in which bit-products are grouped for the first stage of the bit-product reduction process, and (2) it uses a single (4,3) counter, besides the conventional half and full adders, to optimize the reduction process. The proposed method reduces the number of reduction stages when n is equal to 5, 14, 20 or 29 bits. To illustrate this new technique, the complexity and delay to reduce a 14 by 14 bit-product array using the proposed scheme are compared to that of the traditional Wallace multiplier.