Analog IC placement using absolute coordinates and a hierarchical combination of Pareto optimal fronts

Analog integrated circuit (IC) floorplan automation due to its importance has been intensively studied in the last decades. The problem is complex as multiple requirements which appear in the form of device symmetry, matching and proximity constraints must be dealt simultaneously for a robust floorplan. Absolute coordinates is the most intuitive manner of implementing these layout constraints, as it allows for the optimization kernel to move the cells explicitly and represent any possible floorplan. A complete study of previous approaches shows that illegal overlaps have been improperly modeled in a single-objective (SO) cost function for optimization along with other objectives. In this paper, the problem of analog floorplan automation in absolute coordinates is re-formulated, and, since it is impracticable to determine a single best floorplan for all of the design objectives, a multi-objective optimization (MOO) algorithm is applied to solve it. In order to reduce the problem complexity, Pareto optimal fronts (POFs) of placements representing the tradeoffs between the design objectives are combined bottom-up through the partitions of the circuit's hierarchy. The approach is demonstrated for the UMC 0.13μm design process and compared with most recent representations.