A multi-standard interpolation filter for motion compensated prediction on high definition videos

This paper proposes a hardware design for a multi-standard interpolation filter for the motion compensated prediction targeting H.264/AVC and HEVC video coding standards, which can be applied for Fractional Motion Estimation (FME) and Motion Compensation (MC) steps. In this paper it is introduced the fractional samples generation according to these standards, and the differences between them are highlighted. After that, an analysis was made to merge the interpolation filters of both standards, so an optimized hardware design could be proposed. The developed hardware architecture was described in VHDL and synthesized for FPGA and ASIC technologies. The hardware results for the TSMC 65nm ASIC technologies report 5.7K gates with a power consumption of 2.69mW when running at 806.45MHz.