Power-Loss Prediction of High-Voltage SiC-mosfet Circuits With Compact Model Including Carrier-Trap Influences

The paper aims at clarifying the carrier-trapping influence on the electrical characteristics of silicon carbide (SiC) power MOSFETs and its inclusion in the simulation of SiC power
mosfet
-based circuits. Special focus is given on the degradation of the switching characteristics due to carrier trapping at SiC/SiO
₂
interface defects. A compact SiC power
mosfet
model, considering the trap density in the framework of a complete surface-potential description, has been developed by for accurate circuit simulation including power-loss prediction. The carrier trapping is verified to cause a switching delay, which results in switching loss increase. To achieve low power loss, trap-density reduction is shown to be vital. The maximum allowable trap density, which does not affect switching power loss, is discussed.