Low ${\rm VDDmin}$ Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations

The designs of resistive RAM (ReRAM) macros are limited by 1) a small sensing margin, limited read-
${\rm VDDmin}$
, and slow read access time (
$T _{\rm AC}$
) caused by a high cell-resistance and small cell-resistance-ratio (R-ratio) and 2) poor power integrity and increased energy waste attributable to a large SET dc-current (
$I _{\rm DC-SET}$
) resulting from the wide distribution of write (SET)-times (
$T _{\rm SET}$
). This study proposes a swing-sample-and-couple (SSC) voltage-mode sense amplifier (VSA) to enable an approximately
$1.8+{x}$
greater sensing margin for lower
${\rm VDDmin}$
and a
$1.7+{x}$
faster read speed across a wide
${\rm VDD}$
range, compared with conventional VSAs. A 4T self-boost-write-termination (SBWT) scheme is proposed to cut off the
$I _{\rm DC-SET}$
of devices with a rapid
$T _{\rm SET}$
. The SBWT scheme reduces
${\hbox{99}}+\%$
of the
$I _{\rm DC-SET}$
with an area penalty below 0.5%. A fabricated 512 row 28 nm 1 Mb ReRAM macro achieved
$T _{\rm AC} ={\hbox{404 ns}}$
when
${\rm VDD}={\hbox{0.27 V}}$
and confirmed the
$I _{\rm DC-SET}$
cutoff by the SBWT.