Static FRAM: an emerging nonvolatile memory technology

Summary form only given. Nondestructively read ferroelectric memories can be achieved using the ferroelectric material as the FET gate oxide. CMOS FETs with ferroelectric gate oxides are very difficult to build but ferroelectric gate TFTs have a robust process that differs from that of the ferroelectric capacitor by only one mask layer. The static FRAM (SFRAM) is one such device. It consists of a Pt-PZT capacitor where the top Pt electrode is replaced by a semiconducting oxide. The ferroelectric material polarization state modulates the semiconducting electrode conductivity. The magnitude of the conductivity change can be process controlled to range from 3:1 to 300:1 depending on the product requirements. Current sensing amplifiers can detect the transistor state in as little as 15 ns. Combining one CMOS transistor as the pass gate with each SFRAM transistor, large nonvolatile memory arrays can be built with 40 /spl mu/m/sup 2/ cell sizes, <100 ns cycle times, and using simple SRAM asynchronous three line control. Write operations for SFRAM memory cells are identical to those of the FRAM and have similar power consumption. However, SFRAM source and drain contacts are ohmic, allowing read operations using voltages as low as 50 mV and consuming infinitesimal memory array power. The devices exhibit little fatigue or imprint and can operate with V/sub cc/ as low as 3.5 V. Retention, the most difficult factor to control in ferroelectric transistors, has been demonstrated at 70/spl deg/C. The authors describe the fabrication process for SFRAM devices, provide performance data for discrete transistors measured to date, and show design criteria for a 64 kbit SFRAM.