A 42.5 mm/sup 2/ 1 Mb nonvolatile ferroelectric memory utilizing advanced architecture for enhanced reliability

A 1 Mb ferroelectric random access memory (FRAM(R)) with 15.8 /spl mu/m/sup 2/ cell size and 60 ns read/write times incorporates a one transistor-one capacitor (ITIC) architecture. Data retention reliability is improved by the use of a pre-charged ferroelectric capacitor reference, an in-pitch ferroelectric capacitor circuit for wordline boosting, and an optimized sensing scheme. Active power is 50 mW at 5.0 V. PZT capacitors are used with a 0.5 /spl mu/m CMP planarized CMOS process.