4.2 pW timer for heavily duty-cycled systems

An ultra-low energy wake-up timer suitable for heavily duty-cycled systems is presented. A prototype implemented in 0.18μm CMOS consumes 4.2pW of power for 18Hz of oscillation (0.23pJ/cycle). A dynamic 3-stage architecture, duty-cycled current-source, and low operating voltage (0.6V) enabled by a voltage boost circuit all contribute to the improved efficiency.