A 100-GbE reverse gearbox IC in 40nm CMOS for supporting legacy 10- and 40-GbE standards

This paper presents the industry's first low-power 100-Gigabit Ethernet (GbE) multi-link gearbox (MLG) IC, which facilitates transport of independent 10-GbE and 40-GbE signals to 4×25G physical layers implementing 100GBASE-R. The IC consumes only 1.37-W while implementing complicated reverse gearbox functionality. The measured TX jitter from the 25-Gb/s lane is 1.6-ps
_rms
, and the recovered clock jitter is 0.5-ps
_rms
. The measured RX input sensitivity for a BER 10
^-12
is 42-mV
_ppd
. The proposed gearbox IC, fabricated in a 40nm CMOS process, occupies 3.7×3.4-mm
²
. The power consumption of RX and TX in 25G interfaces are 47-mW and 51-mW, respectively, and those of a 10G interfaces are 24-mW and 25-mW, respectively. Gearbox functionalities are verified with embedded self-test logics.