Read back scrubbing for SRAM FPGAs in a data processing unit for space instruments

SRAM-based FPGAs like Xilinx Virtex FPGA offer the highest processing capability currently available as radiation tolerant space qualified parts. However their configuration memory is not radiation hardened, monitoring and correction of configuration is required to prevent upsets from affecting operation. This paper presents a setup in which a controlling processor has access to the configuration interface and performs the task of configuration memory monitoring and error scrubbing. As blind scrubbing that is simple over writing of the configuration memory may cause erroneous internal contention, read back scrubbing is discussed. Read back scrubbing in turn creates a high load on the processor, so a method is presented in which the read back is still physically performed, but the processor does not have to perform the task of inspecting the read back data for upsets. Instead the frame ECC core which is inside the Xilinx SRAM FPGAs performs checksum calculation for read back data and flags errors. Thereby unlike in a complete implementation of the scrub controller in FPGA logic the software still maintains full control, but creates less processor load. Furthermore this setup uses the JTAG interface which has the lowest cross section for radiation induced error compared to other configuration interfaces.