A new SOI MOSFET for low power applications

SOI devices have attracted a great deal of interest due to their inherent advantages for low power and high performance applications. Assaderaghi et al. proposed the DTMOS (dynamic threshold-voltage MOSFET) for ultra-low voltage VLSI applications (1997). Several researchers proposed a modified SOI MOSFET with the channel body connected to the drain through a small auxiliary MOSFET (Chung et al. 1996; Houston, 1997) to increase the operating voltage. In this paper, we propose a new SOI MOSFET with an auxiliary MOSFET in which the gate and drain are shorted to the gate of the main transistor and the source is connected to the channel body of the main transistor. This auxiliary transistor applies a positive bias to the channel body of the main transistor. In this paper, we present some experimental data and compare the proposed device with a conventional MOSFET, a DTMOS, and the modified SOI MOSFET proposed by Chung et al.