Multithreading implementation in a single core TMS320C6713 DSP

Very Long Instruction Word is an architectural breakthrough in DSP architecture that caters to the real time constraints and efficient algorithm implementation. This paper brings out various loopholes namely latency, underutilization of functional units, use of NOPs and constraints of cross path in register file accessing present in such architecture. This paper proposes a technique to reduce the delay slots present in the pipeline due to NOPs and hence obtain reduction in code size and reduced latency. With the available functional units, thread level parallelism is introduced to enhance existing instruction level parallelism, thus addressing the issue of under utilization of functional units. Aforementioned issues are dealt with by the use of multithreading - concept frequently associated with multi-core DSPs and RTOS. This paper reports a novel technique of introducing a programming discipline in assembly coding to emulate multithreading in a single core DSP without use of OS and reduction in the number of clock cycles required is observed. Code snippets implemented using Code Composer Studio for TMS320C6713 illustrate the concepts.