A VHDL-based simulation methodology for estimating switching activity in static CMOS circuits

Recently, power dissipation has become a major design constraint for complex VLSI circuits. Designers need tools that rapidly, but accurately, estimate power dissipation in a given design. Two categories of tools are useful for this purpose: (1) power optimization tools and algorithms tightly integrated with logic optimization, and (2) an analysis tool for estimating the power consumption in an existing netlist. This work addresses the latter issue by employing a VHDL-based approach for analysis of power consumption in static CMOS combinational logic designs. The circuits under test will be either the result of logic synthesis with various optimization constraints or hand designs done through schematic capture. The proposed approach will also be used to analyze various known architectures of the same network for power consumption, such as various forms of adders. The work presented in this article consists of three phases: (1) designing smart VHDL simulation models that first measure transition activity at each node of the netlist and then estimate the power based on this activity and on fanout at each node, (2) the generation of smart input stimuli that achieve an upper bound on transition activity and hence power consumption, and (3) analysis of different topologies of the same circuit. The estimates produced by this analysis may provide useful feedback to designers or synthesis tools, allowing for better exploration of the design space.