A sample preparation methodology to reduce sample edge unevenness and improve efficiency in delayering the 20-nm node IC chips

With continuous scaling of Complementary Metal Oxide Semicondutor (CMOS) device dimensions, traditional inter-level dielectrics have be replaced by low-k materials, because of the advantages of ultra low-k material such as lower parasitic capacitance, lower cross talk effects, and lower RC delay. The new material in integrated circuits (IC) makes physical failure analysis (PFA) more challenging. This paper presents a sample preparation methodology for reducing the sample deprocess edging effect with an efficient way on delayering the 20-nm node IC chips. We combined several delayering techniques to achieve an excellent flatness surface and improve the time efficiency for PFA on 20nm technology.