Fast and accurate fractional frequency synthesizer in 0.18μm technology

A 900MHz frequency synthesizer is presented in this article. The purpose of the proposed architecture is to minimize lock time in Phase-Locked Loops (PLLs). The structure has been simulated by HSPICE software in a typical 0.18um CMOS technology at the supply voltage of 1.8V. Simulation results prove that the designed frequency divider locks instantly that is a lower lock time compared to conventional PLLs.