Measurement of de-assertion threshold of power-on-reset circuits

A test circuit for measuring the de-assertion threshold of a Power-on-Reset (POR) circuit is presented. With the help of the test circuit, POR de-assertion voltage can be measured without requiring a dedicated analog pad or a supply voltage higher than the POR supply voltage. The test circuit does not impact the normal mode of operation of POR and the area and power overhead due to the addition of the test circuit are minimal. The test circuit has been designed and simulated in 28nm CMOS technology. The simulation results show that the maximum error in de-assertion threshold measurement is less than +/− 0.5%.