40 Gb/s FPGA implementation of a reduced complexity volterra DFE for DQPSK optical links

A low complexity MIMO Volterra Decision Feedback Equalizers (VDFE) for optical transmission systems employing NRZ-DQPSK signalling is proposed. Based on a comparative study performed by means of simulations, it is proved that the proposed equalizers maintain the required efficiency in terms of BER, achieving significant reduction in terms of complexity. Also, suitable architectures for high-speed FPGA implementations are presented. A 8-input 2-output low complexity VDFE involving three taps feed-forward filtering and two taps backward filtering was implemented on a single state-of-the-art FPGA. The target rate of 40 Gb/s is achieved by applying extensive pipelining and parallelism and fully exploiting specific FPGA features.