Design of a 5-bit, 4.87GS/s, 240µW Flash ADC using a MUX-based decoder with Regenerative Buffer in 45-nm CMOS

This paper presents a 5 - bit 4.87GSps Flash ADC design using 45-nm GPDK CMOS technology library. The designed system consists of two main blocks as comparator array and digital decoder. The digital decoder contains 2∶1 MUX based 1 - of - N decoder and Regenerative Buffer units. As a result, active die area and the power consumption are reduced in addition to increase in sampling frequency. The power supply voltage range for the overall system is ± 1.8V. The simulation results include maximum power consumption of 0.24 mW. The Conversion time 204p sec, the measured DNL and INL to less than 0.02LSB and 0.1LSB.