High throughput feed forward pipelined parallel architecture for FFT and IFFT

This paper presents a novel approach to develop pipelined architectures for fast Fourier transform (FFT) and Inverse fast Fourier transform (IFFT). For reducing area and time complexity, the architectures use hard wired Twiddle factor storage and new switching circuit for complex multiplication and that is employed in four point FFT/IFFT architectures. Pipelined Architectures for complex valued fast Fourier transform and Inverse fast Fourier transform are derived. This projected design is intended based on feed forward designs and may be extended to any radix 2
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based FFT/IFFT algorithm to extend the throughput. The projected FFT/IFFT design was synthesized by Synopsys design Compiler using the TSMC 90-nm library, and also the projected designs provide less latency and high Throughput than the reference FFT design. The design also synthesized for various Xilinx field-programmable gate-array platforms that also shows comparable results.