SiO2 Free HfO2 Gate Dielectrics by Physical Vapor Deposition

HfO
₂
layers, 25-Å thick, were grown by cyclic Hf sputter deposition and room temperature oxidation steps on chemically oxidized Si(001). Subsequent in situ annealing and TiN deposition yield a high-κ gate-stack for which the original 8-Å-thick SiO
₂
layer is eliminated, as confirmed by transmission electron microscopy. Transistors fabricated with this gate-stack achieve an equivalent oxide thickness in inversion T
_inv
=9.7 Å, with a gate leakage J
_g
=0.8 A/cm
²
. Devices fabricated without in situ annealing of the HfO
₂
layer yield a T
_inv
which increases from 10.8 to 11.2 Å as the oxidation time during each HfO
₂
growth cycle increases from 10 to 120 s, also causing a decrease in J
_g
from 0.95 to 0.60 A/cm
²
, and an increase in the transistor threshold voltage from 272 to 294 mV. The annealing step reduces T
_inv
by 1.5 Å (10%) but also increases the gate leakage by 0.1 A/cm
²
(30%), and causes a 61 mV reduction in V
_t
. These effects are primarily attributed to the oxygen-deficiency of the as-deposited HfO
₂
, which facilitates both the reduction of an interfacial SiO
₂
layer and a partial phase transition to a high-κ cubic or tetragonal HfO
₂
phase.