High-speed analog processing for real-time fault location in electrical power networks

This paper explores the potential and limitations of analog integrated circuit techniques for the simulation of low-loss or lossless 1D or 2D transmission mediums. In this approach, a transmission line is mapped into a ladder consisting of N identical LC elements, each modeling a finite length increment of the line. Inductors are then emulated by a gyrator-capacitor combination, yielding a classical transconductor-capacitor (gm-C) circuit, suitable for integration. The validity of this approximation is discussed in the context of fault location in power networks, an application based on the electromagnetic time-reversal method. Design constraints on gm-C circuits are derived and non-ideal effects such as finite open-loop gain and component mismatches are evaluated. It is shown that a simple analog implementation can locate the fault within 1% accuracy with a significant speed advantage over classical computational methods, reducing the processing time to less than 100ms.