Gate tunable resonant tunneling in graphene-based heterostructures and device applications

Electron tunneling is receiving increased emphasis as the physical mechanism of operation in emerging devices that seek to mitigate power dissipation issues in aggressively scaled CMOS technology. A tunneling field-effect transistors (TFET) consisting of a gated p-i-n junction is arguably the best known example. In a separate class of tunneling devices, consisting of two semiconducting layers separated by a barrier, the inter-layer tunneling current-voltage characteristics possess gate-tunable negative differential resistance [1]–[3], which is subsequently used to implement Boolean logic functions [4]. We describe here the fabrication, characterization, and benchmarking of inter-layer TFETs (ITFETs) using double bilayer graphene heterostructures separated by hexagonal boron-nitride dielectric as example [Fig. 1(a)].