Subtractive plasma-etch process for patterning high performance ZnO TFTs

Fig 2 shows a cross sectional SEM image of the channel area after etching tungsten prior to stripping the PMMA etch mask. The thickness of the ZnO film measured ∼52 nm, both in the channel area and underneath the source/drain pads, indicating that the ZnO film was not thinned during the plasma-etch process. Fig 3(a) and (b) show the I
D
-V
D
output characteristics of a ZnO TFT with a 155 nm and 425 nm channel, respectively. The maximum observed drain current density (I
D
) and transconductance (g
m
) for the 155 nm devices was 830 mA/mm and 121 mS/mm, respectively. However, the devices do not saturate at high V
D
values, due to lateral breakdown limitations of the short channels. Fig 3(c) shows I
D
plotted as a function of V
G
on both a log- and linear-scale for devices operating in the linear region with measured channel lengths of 155, 215, 325 and 425 nm. The devices show a near linear dependence on I
D
versus L
C
. However, a negative shift in the on-voltage (V
on
), defined as the gate voltage when I
D
begins its initial increase the log(I
D
)-V
G
plot [4] is observed as L
C
is decreased. Fig 4(a) shows the extracted on-resistance (R
on
) plotted as a function of channel length. From the data, the total parasitic source/drain resistance (R
SD
) can be extracted by gated-TLM method [5], shown in Fig 4(b). The devices exhibit a width normalized R
SD
of 2.1 Ω·mm indicating the tungsten/ZnO interface resistance is low.