Improve LLC Bypassing Performance by Memory Controller Improvements in Heterogeneous Multicore System

The shared last-level cache (SLLC) in heterogeneous multicore system is an important memory component that shared and competitive between multiple cores, so how to improve the SLLC performance has become an important research area. Last-level cache (LLC) bypassing technique that bypasses the LLC a part of memory requests is one of the most effective methods. The bypassed requests are sent directly to off-chip main memory (DRAM) rather than eliminated. We find that the bypassed requests influence the original scheduling sequence in Memory Controller (MC) severely. Besides, immoderate bypassing will disturb the MC load balance. We propose a 3-step method memory that adjusts memory scheduling algorithm to optimize LLC bypassing performance. The first step is adding an independent bypass stream for bypassed requests. The second step is scheduling the bypass stream with a smaller probability than that of normal GPU stream. The third step is adding a guard mechanism for MC. By dynamically set and revoke the guard, we can avoid unbalanced bypassing. For case study, we applied the 3-step method on two modern memory schedulers. The experimental results show that after applied the 3-step method, the schedulers improve the system performance obviously.