A 10-bit 50-MS/s SAR ADC for dual-voltage domain portable systems

The analog-to-digital converter (ADC) is an essential component providing the interface between the sensed analog signal and the corresponding digital representation for a portable ultrasonic systems. In order to extend the battery life for the portable system, a low-voltage ADC is crucial for saving the power. However, the sensed analog signal is usually larger than the tolerable range of a low-voltage ADC. A level shifter, which possibly consumes more power than ADC, is therefore adopted to solve this problem. This paper presents a 10-bit 50-MS/s successive approximation register (SAR) ADC by manipulating simple but effective circuit design techniques to operate at dual-voltage domain without the need of an additional level shifter for shrinking the input signals. Particularly, we propose a technique to implement the ADC with 3.3-V I/O devices and 1.2V MOS transistors. The proof-of-concept design was fabricated in TSMC 130-nm 1P8M CMOS technology. It consumes 1.6 mW at a 50 MS/s sampling frequency and about 2 MHz sinusoidal input signal with 1.65V input common-mode voltage and 2Vp-p differential input amplitude. The measurement result shows an ENOB of 9.15 bits, and both the DNL and INL are within 1 LSB. The active area is 0.226 mm
²
.