Performance evaluation of hierarchical NoC topologies for stacked 3D ICs

Three-Dimensional (3D) integrated circuits (ICs) have emerged as a solution to attend the demand of high performance, low power and high density of the MultiProcessors Systems-on-Chip (MPSoCs). However, some important issues need to be observed in the interconnection device for 3D designs. In this paper we have presented the advantages of the 3D-HiCIT network-on-chip (NoC) when compared to other hierarchical topologies in terms of flexibility, scalability and performance. Considering all constraints of this new scenario of circuit integration, the proposed hierarchical 3D NoC verified in this work meets well with the reality of these designs, presenting gains in several aspects.