On-chip jitter tolerance measurement technique for CDR circuits

We propose an on-chip circuit technique to characterize jitter tolerance of binary clock and data recovery (CDR) circuit. The proposed jitter modulation scheme incorporates modulating-charge-pump and pulse-generator circuits to apply a periodic triangular voltage directly to the control voltage. The range of the modulated jitter amplitude is 0.05-2 UIpp at 10 MHz, and the frequency range is 100 KHz-20 MHz. The CDR circuit was fabricated in 65 nm CMOS, and the jitter tolerance was successfully measured at 5 Gbps with a 2⁷-1 PRBS pattern, The accuracy is within 23% of the theoretical limit. The whole CDR circuit consumes 29.9mW at a supply voltage of 1.2 V.