A flipped voltage follower based analog multiplier in 90nm CMOS process

In this paper, a five transistor voltage adder, consisting of a flipped voltage follower devised to work in low voltage rail, has been used as the main building block for designing an analog multiplier. Four of such cells have been used for biasing and signaling. This Multiplier has been designed using GPDK 90nm CMOS technology and simulated in Cadence Spectre environment. The supply voltage has been taken as 1-Volt. In worst case the multiplier consumes 178 μW power and perfectly working up to 454.56 MHz with less than 1.5% harmonic distortion components.