Novel method for detecting bitline contact misalignment using quantitative analysis of high-aspect ratio SEM images

Bitline contact misalignment has a negative impact on yield in 20nm and sub-20nm NAND technology, which is typically worse at a wafer's edge than at its center. We hypothesized that photo critical dimensions (CD) and/or registration issues were contributing factors to this misalignment issue, potentially caused by incoming wafer CD, incoming wafer edge topology, and photolithography scanner mismatch. Because traditional optical and electron beam (e-beam) inspection tools cannot detect bitline contact misalignment, which is made even worse with high-aspect ratio (HAR) contacts, production wafers must currently be scrapped for physical failure analysis (PFA) x-section as a means of inline process control and compensation. Detection of bitline HAR contact misalignment requires the ability to resolve the bottom of the contact with the surrounding shallow trench isolation (STI) and silicon structure. In this paper, we show that the preferred approach is to use a high-resolution scanning electron microscope (SEM) capable of HAR imaging.