Inspection challenges for triple patterning at sub-14 nm nodes with broadband plasma inspection platforms

With the continuous shrink of technology nodes, lithography becomes more and more challenging. At 20 nm node, double patterning technology (DPT) was the usual way of achieving the fine device structures. Until EUV is available as a high volume manufacturing (HVM) solution, DPT or triple patterning technology (TPT) will be required to sustain scaling. However, as the industry goes forward with scaling, for sub-14 nm nodes the chip manufacturers are anticipating three or four masks per layer. Exposing the patterns separately allows the spacing or pitch of the structures to be reduced by a factor of two (or more for triple/quadruple patterning) while increasing the metrology and inspection challenges. As with many of the previous geometry shrinks, there will be the usual concerns about yield and reliability. In order to control and predict yield for sub-14 nm nodes we show that design information when integrated with inspection platforms can help predict design weak spots efficiently. It is the purpose of this paper to elucidate some of the inspection challenges and solutions for sub 14nm device structures.