Vertical integration of memristors onto foundry CMOS dies using wafer-scale integration

As Moore's law scaling approaches its physical limit, there is increased interest in memristors as a replacement to transistors in memory applications due to their smaller footprint and superior scaling characteristics. However, memristors are intrinsically two-terminal devices, requiring an underlying CMOS control interface for proper operation. Thus the integration of CMOS and memristors is essential to the development of memristor technology. Accordingly, hybrid configurations have been proposed that make use of the advantages of CMOS while utilizing a high density of memristors. However, memristor/CMOS hybrid fabrication is not trivial because high-density memories require memristor dimensions to be much smaller than those of the underlying CMOS. Additionally, memristors typically make use of materials not allowed in conventional CMOS fabrication. These issues point to a post-CMOS fabrication approach. An associated consideration for memristor/CMOS hybrid fabrication is the high cost of whole wafer fabrication. While whole wafer fabrication of memristors is viable for large volume markets, it is not a practical route for niche applications or research. While this suggests the use of CMOS dies, edge effects typically set the minimum processable die size, as in the case of edge beads, which limit the achievable resolution of devices. To address these issues, we present a hybrid integration approach for post-CMOS vertical integration of memristors that is independent of CMOS die size. Our approach enables the vertical integration of memristors with small foundry-fabricated dies using a waferscale integration scheme. We demonstrate this approach using a 2.2-mm × 3.2-mm CMOS die fabricated in a standard dualpoly, three-metal 0.5-μm technology process. We use solution-processed BCB as an adhesive to embed CMOS dies into silicon wafer handles, allowing for easy handling and compatibility with a variety of lithography techniques such as electron-beam, nanoimprint and photolithography. The process is compatible with spin-coated planarization layers, such as polyimide or BCB, if nanometer-scale roughness is desired. As a demonstration, vertically integrated Ag/SiO
₂
/Pt switches were fabricated on CMOS using conventional photolithography techniques in a university cleanroom and tested through the CMOS circuitry. The measurements were compared to those of Ag/SiO
₂
/Pt switches fabricated off-chip in a similar process and indicate that the memristor/CMOS hybrids were fully functional. We believe this hybrid approach will pave the way for hybrid CMOS-memristor chips, enabling applications from neuromorphic computing to high-density memories.