Evolution of nanoscale silicon CMOS technology for ultra low power application

Nanoscale silicon CMOS technology aimed for ultra low power application is presented. The characteristics variability and noise of FinFETs are dramatically suppressed by introducing an amorphous metal gate, and the suppression is beneficial both for scaling and reduction of power consumption. A tunnel FET (TFET) is also promising candidate to reduce the power consumption dramatically. The current drivability of a silicon TFET is improved significantly by introduction of a fin-type 3D structure and novel trap engineering.