Real-time software video encoder on a multimedia RISC processor

A real-time software MPEG1 video encoder on a multimedia RISC processor, V830R/AV, is presented. The V830R/AV processor provides 64-bit SIMD media-enhanced instructions. The motion estimation is accelerated by a combination of the partial absolute difference instruction and a method to sum up partial block differences. The IDCT in conformity with the IEEE standard is simply implemented by the multiply-accumulate instruction with symmetric rounding. The encoder program structure is carefully reconstructed to reduce instruction cache misses, which heavily degrade the processor performance. Preload instructions are used to load data to the data cache in parallel with successive instruction execution. Consequently, the cache miss penalties are drastically reduced. The current version of the software MPEG1 video encoder on the 200 MHz V830R/AV processor encodes SIF (352/spl times/240 pels) video at 30 frames/s with I, P and B picture types in 193 M clocks/s.