Statistical design of a multiplier using a low power square-law CMOS analog cell

The statistical design of a new multiplier using the square-law characteristics of MOS transistors in the saturation region is discussed in this paper. The multiplier is statistically robust and has a good yield. Initial simulation results of the circuit have been given and the offset current and nonlinearity of the multiplier have been statistically examined. Response Surface Methodology and Design of Experiments techniques were used as statistical VLSI design tools combined with the statistical MOS model. Device size optimization and yield enhancement have been demonstrated.