Parasitics in Power Electronic Modules: How parasitic inductance influences switching and how it can be minimized

This paper covers a theoretical approach on understanding the impact of parasitic inductances in power modules. Simulations provide a fundamental insight into the influence of parasitic inductances on the maximum switching speed, i.e. the minimum voltage rise time. Based on this, strategies for parasitic inductance minimization are outlined. The concept of multilayer copper thick-film substrates is illustrated by a sample design.