Overshoot cancelation of residue voltage in fully differential comparator-based pipelined ADC

This paper presents a new method to cancel out the overshoot of the residue voltage in a fully differential comparator-based pipelined ADC. In this ADC, a fully differential capacitive gain doubler is used in the first stage as multiplying digital-to-analog converter (MDAC). Since the first stage cannot drive large capacitive loads, therefore a topology with high input impedance is chosen for the second, third and following stages. This topology does not require the common-mode feedback (CMFB) circuit. The proposed 10-bit pipelined ADC has been designed and simulated in a 90 nm CMOS technology. Simulation results show that the ADC achieves SNDR of 55.6 dB and SFDR of 64.5 dB at sampling frequency of 100 MS/s and consumes 2.8mW from a 1V power supply.