Demonstration of an FPGA controller for guaranteed-rate optical packet switching

A switch controller which achieves low-latency deterministic `Guaranteed-Rate' (GR) connections in packet switched networks is demonstrated on a `Field Programmable Gate Array' (FPGA) device. A Software Defined Networking (SDN) control plane can configure the FPGA controllers to establish deterministic GR connections in a forwarding plane of IP routers or layer-2 packet switches. The use of deterministic GR connections can reduce queueing delays to negligible values, so that the end-to-end delays are reduced to the fiber latency. The switch controller can operate routers, switches and links at 100% loads, while simultaneously guaranteeing very low end-to-end queueing delays. A testbed consisting of 8 switches in a linear array is synthesized on an Altera Cyclone IV FPGA. An SDN control plane routes 128 traffic flows through the testbed to saturate the switches and links. Packets move through the forwarding plane at a clock rate of 52 MHz, transferring millions of packets per second, and statistics are recorded. The demonstration shows that all traffic flows in the testbed achieve deterministic GR service. The FPGA demonstration is accompanied by a video which visually illustrates packet forwarding in the network. The GR technology applies to IP routers and layer 2 packet switched networks, with thousands of nodes spanning arbitrary distances. The FPGA controller also applies to layer 2 MPLS (Multiprotocol Label Switching) and Ethernet switches, and to `Optical Packet Switched' networks, to achieve deterministic GR services and to operate links at 100% loads.