The Virtual Test program (VTest)

The purpose of the USAF's Research Laboratory's Virtual Test (VTest) Program is to develop methodologies and software tools that permit the design, capture, and simulation of tester independent test requirements, Unit Under Test(UUT) models, and tester resource description information for the purpose of virtual testing. The program has resulted in a set of Integrated Commercial Off-The-Shelf(COTS) tools that reuse design simulation models developed for Electronic Design Automation (EDA) tools for test simulation on new digital Printed Circuit Boards (PCBs) and Assemblies (PCAs) and to significantly reduce model development on current digital PCAs. EDA derived tools are used to lay out and simulate a virtual test schematic (includes models of the UUT and tester environment) for the development of fully simulated analog/mixed signal Test Program Sets (TPSs), thereby significantly reducing analog/mixed signal TPS test integration times. Observed savings for various portions of the TPS development process vary from 24% for New Design Digital TPSs to 85% for Rehost of Analog TPSs.