A novel asymmetrical SRAM cell tolerant to soft errors

In this paper, we propose a novel asymmetrical 11T SRAM cell design that has fault correction capability. In addition, the Layout design through Error-Aware transistor Positioning (LEAP) technique is adopted in designing the layout of this proposed 11T cell. The area of the proposed 11T cell without using LEAP technique (regular 11T) is 76% larger than that of traditional 6T cell and 16% larger than that of the Quatro cell. The area of 11T cell with LEAP technique (LEAP-11T) is 15% larger than that of regular 11T cell and 103% larger than that of 6T cell. Simulation results show that the error cross section of regular 11T is 17X lower and 2.8X lower than that of traditional 6T at LET = 10 and 30 MeV-cm
²
/mg respectively in normal strikes; and it is 2.2X lower than Quatro cell when LET = 30 MeV-cm
²
/mg in normal strikes. With LEAP technique implemented, the LEAP-11T cell's error cross section is 6.5X lower than the Quatro cell when LET = 10 MeV-cm
²
/mg in angled strikes.