A TSV to TSV, A TSV to Metal interconnects, and A TSV to active device coupling capacitance: Analysis and recommendations

In this paper, we analyzes the coupling capacitance between TSV-TSV, TSV-Metal interconnects, and TSV-Active device. This paper presents a complete analysis of coupling capacitance of TSV-TSV structures. As TSV parasitic capacitance is less than other conventional IO structures' capacitance, therefore TSV technology results in lower I/O power consumption, which makes it suitable for low power applications. The electrical characteristics of coupling between TSVs and metal lines in 3D-ICs are also analyzed. The simulation results for the electrical characteristics of the coupling between TSVs and metal lines in 3D-ICs show that the coupling is not negligible when TSV is relatively short compared to the TSV width. High-speed signals on TSVs can interact with the active device area through a lossy substrate, causing circuit malfunctioning and signal integrity problems, i.e., TSVs can act as a major noise source throughout the substrate. Therefore, understanding the impact of TSV proximity on MOS transistor performance is critical for integration with active circuitry without performance degradation. In this paper, noise coupling between TSVs and CMOS is investigated. The results show that 3D integration process has no impact on CMOS technology, or very limited effect. Several isolation techniques are also proposed.