Low-power operation of InP-based DHBT's for high bit rate circuit applications: reduction of saturation voltage (V/sub sat/)

An important doping level of quaternary layers and a thin collector thickness is experimentally shown to improve electron transport properties in base-collector junction of InP/InGaAs/InGaAsP Double Heterojunction Bipolar Transistors (DHBTs) and also to yield a small saturation voltage (V/sub sat/). We have fabricated InP/InGaAs/InGaAsP-InP DHBT's with very low Vsat (0.8 V) by increasing the grading layers doping level (5.10/sup 16/ cm/sup -3/), optimizing the spacer layer thickness (30 nm) and reducing both the collector area and thickness (350 nm). This latter characteristic was compensated for in terms of base-collector capacitance (C/sub BC/) by a collector area reduction (over-etching). Those optimizations do not induce any degradation of static and dynamic transistor performances: static gain=78, BVce=9 V, F/sub t/=80 GHz and F/sub max/=60 GHz for a DHBT with emitter-base area S/sub EB/=4/spl times/11 /spl mu/m/sup 2/.