Logic synthesis of assertions for saftey-critical applications

In this work we propose the rather new approach to synthesize properties formulated in verification languages, in particular PSL, down to hardware level. Such flow can be useful especially for safety-critical applications to automatically generate runtime monitors at little additional design efforts. Existing assertion synthesis tools from both academia and industry are presented as well as evaluation results concerning their features and drawbacks. The main part of this work focuses on the development of a proposed own tool flow which could benefit from available commercial and/or open-source tools like PSL parsers and equivalence checkers. The paper concludes with an outlook to future work in order to smoothly integrate our proposed approach into an existing state-of-the-art FPGA design flow. First resource estimations from previous work showed that optimized hardware assertion checkers may make up only a few percentage of the designs complete size.